Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon based Complementary Silicon-Oxide Semiconductor (CMOS) with MTJ technology, is a technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc. MRAM is now a proven nonvolatile memory technology with many advantages over other commercialized memory types in terms of writing/read speed, power consumption, lifetime, etc. However, conventional MRAM has a fundamental limitation of scalability. STT-MRAM not only possesses the major benefits of conventional MRAM but also has tremendous potential for scalability. Unlike conventional MRAM that requires a separate word line in addition to a BIT line to switch the magnetization direction of a free layer in a MTJ, STT-MRAM relies only on a current passing through the MTJ to rotate the free layer magnetization direction. In order for STT-MRAM to switch a bit, however, the current density passing through the MTJ device should be larger than a critical switching current density (Jc). Since current density is inversely proportional to device physical size given a fixed amount of current, the switching efficiency increases as the CD size of the MTJ decreases. Thus, CD is normally quite small for a STT-MRAM and is typically less than 100 nm in size.
A MTJ element may be based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In a MRAM device, the MTJ element is formed between a bottom electrode such as a first conductive line and a top electrode which is a second conductive line. A MTJ stack of layers that is subsequently patterned to form a MTJ element may be formed in a so-called bottom spin valve configuration by sequentially depositing a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer. The AFM layer holds the magnetic moment of the pinned layer in a fixed direction. In a MRAM MTJ, the free layer is preferably made of NiFe because of its reproducible and reliable switching characteristics as demonstrated by a low switching field (Hc) and switching field uniformity (σHc). Alternatively, a MTJ stack may have a top spin valve configuration in which a free layer is formed on a seed layer followed by sequentially forming a tunnel barrier layer, a pinned layer, AFM layer, and a capping layer.
The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer that is also magnetized in the “y” direction. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. In a read operation, when a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers otherwise known as a current perpendicular to plane (CPP) configuration, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer from a “1” to a “0” or from a “0” to a “1”. In conventional MRAM, this process is accomplished by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. Alternatively, in STT-MRAM, spin torque magnetization switching is used. Spin transfer (spin torque) magnetization switching has been described by J. Sloneczewski in “Current-driven excitation of magnetic multilayers”, J. Magn. Materials V 159, L1-L7 (1996), and by L. Berger in “Emission of spin waves by a magnetic multiplayer traversed by a current” in Phys. Rev. Lett. B, Vol. 52, p. 9353. The spin-transfer effect arises from the spin dependent electron transport properties of ferromagnetic-spacer-ferromagnetic multilayers. When a spin-polarized current transverses a magnetic multilayer in a CPP configuration, the spin angular moment of electrons incident on a ferromagnetic layer interacts with magnetic moments of the ferromagnetic layer near the interface between the ferromagnetic and non-magnetic spacer. Through this interaction, the electrons transfer a portion of their angular momentum to the ferromagnetic layer. As a result, spin-polarized current can switch the magnetization direction of the ferromagnetic layer if the current density is sufficiently high, and if the dimensions of the multilayer are small. The difference between a STT-MRAM (also known as Spin-RAM) and a conventional MRAM is only in the write operation mechanism. The read mechanism is the same.
Referring to FIG. 1, a memory cell 1 of a STT-MRAM includes a MTJ 13, word line (WL) 6, bit line (BL) 14, bottom electrode 7, and a CMOS transistor having a source 3, drain 4, and p-type semiconductor 2, for example, that provides current for switching the MTJ free layer 11. There is also a bottom electrode 5. Additional layers in the MTJ 13 are an AFM layer 8, pinned layer 9, insulating barrier 10, and capping layer 12.
A critical current for spin transfer switching (Ic), which is defined as [(Ic++|Ic−|)/2], for the present 180 nm node sub-micron MTJ having a top-down area of about 0.2×0.4 micron, is generally a few milliamperes. The critical current density (Jc), for example (Ic/A), is on the order of several 107 A/cm2. This high current density, which is required to induce the spin-transfer effect, could destroy a thin insulating barrier 10 such as AlOx, MgO, or the like. In order for spin-transfer magnetization switching to be viable in the 90 nm technology node and beyond, the critical current density (Jc) must be lower than 106 A/cm2 to be driven by a CMOS transistor that can typically deliver 100 μA per 100 nm gate width. For STT-MRAM applications, the (ultra-small) MTJs must exhibit a high tunnel magnetoresistance ratio (TMR or dR/R) much higher than the conventional MRAM-MTJs that use AlOx as a barrier layer and have a dR/R of about 40% as stated by Z. Diao et. al in “Spin transfer switching and spin polarization in MTJ with MgO and AlOx barrier”, Appl. Phys. Lett, 87, 232502 (2005). D. Djayaprawira et. al in “230% room temperature magnetoresistance in CoFeB/MgO/CoFeB MTJ”, Appl. Phys. Lett. V 86, p. 092502 (2005) demonstrated that a highly oriented (001) CoFeB/MgO/CoFeB MTJ is capable of delivering dR/R>200%. Therefore, it is essential to find a way to combine a high TMR ratio of a CoFeB/MgO/CoFeB MTJ and the current driven switching capability necessary to make Spin-RAM (STT-MRAM) a practical technology.
To apply spin-transfer switching to MRAM technology, it is desirable to decrease Ic (and its Jc) by more than an order of magnitude so as to avoid an electrical breakdown of the MTJ device and to be compatible with the underlying CMOS transistor that is used to provide switching current and to select a memory cell. MagIC has previously disclosed an improved MTJ structure for a STT-MRAM device in a related application HMG06-042/51.
A routine search of the prior art was conducted and the following references were found. Hosomi et al. in “A novel non-volatile memory with spin torque transfer magnetization switching: Spin-RAM”, 2005 IEDM, paper 19-1, present a Spin-RAM with spin-torque transfer magnetization switching for the first time and the device was fabricated with a Co40Fe40B20/RF sputtered MgO/Co40Fe40B20 (pinned layer/tunnel barrier/free layer) MTJ configuration. MTJ size is 100 nm×150 nm with an oval shape. A tunnel barrier layer is made of crystallized (100) MgO whose thickness is controlled to <10 Angstroms for the proper RA of about 20 ohm-μm2 while dR/R or TMR (intrinsic) of the MTJ is 160%. Using a 10 ns pulse width, the critical current density, Jc, for spin transfer magnetization switching is about 2.5×106 A/cm2 which means Ic is equal to 375 μA. Due to a very small MTJ size, resistance distribution of Rp (low resistance state) and Rap (high resistance state) has a sigma (Rp_cov) around 4%. Thus, for a read operation, TMR (without bias)/Rp_cov=40 and this ratio is equivalent to that for a conventional CoFeB/AlOx/NiFe (pinned layer/tunnel barrier/free layer) MRAM MTJ configuration in which TMR is typically 40% with an Rp_cov of around 1.
A spin transfer magnetization switching of a CO60Fe20B20/MgO/Co60Fe20B20 MTJ is reported by Y. Huai et al. in “Spin transfer switching current reduction in magnetic tunnel junction based dual filter structures” in Appl. Physics Lett., V 87, p. 222,510 (2005). The nominal MTJ size is 125 nm×220 nm with an RA of ˜50 ohm-μm2 and dR/R=155%.
Referring to FIGS. 2, 3a-3b, and 4a-4b, a prior art process sequence for patterning a MTJ 20 is illustrated. In FIG. 2, a MTJ stack of layers is shown that has a bottom spin valve configuration, for example, in which an AFM layer 24, pinned layer 25, tunnel barrier layer 26, free layer 27, and capping layer 28 are sequentially formed on a bottom conductor 23 which has been laid down on a substrate comprised of a dielectric layer 22 and via 21. FIG. 3a depicts a patterned photoresist layer 29 formed on a top surface of capping layer 28 from a cross-sectional view and FIG. 3b is a top-down view of the photoresist pattern having a first dimension a1 along an x-axis direction and a second dimension b1 along a y-axis direction. FIG. 4a shows a cross-sectional view of MTJ 20 after the photoresist pattern is etched transferred through the MTJ stack of layers 24-28 and photoresist 29 is stripped. FIG. 4b shows the MTJ 20 in FIG. 4a from a top view where hard mask 28 has dimensions a2 and b2 that are not necessary equal to a1 and b1, respectively, depending on etch conditions.
The fabrication process of a STT-MRAM is very challenging because of the small MTJ size where both easy-axis and hard axis dimensions must be controlled for optimum performance. In a CMOS process, the critical CD control for isolated and dense line features is in one dimension only and there are many well developed methodologies to control iso/dense CD for different applications. However, in MRAM processing, the critical CD involves a post (island) where a length along an easy-axis direction and a width along a hard-axis direction must simultaneously be controlled. Very little is understood in photolithography in terms of how to best control CD in a post pattern. Not only is dimensional control in an x-y plane crucial, but the thickness of the photoresist pattern in a z-direction plays an important factor. If the resist thickness is increased to provide extra process latitude for a subsequent etch step, then the aspect ratio (thickness/CD) may become too large and the post could collapse during image development. On the other hand, if the photoresist thickness is made thinner to allow smaller features to be printed with a larger process window without image collapse, then there may not be enough photoresist to serve as an adequate etch mask during a subsequent etch step where the photoresist pattern is transferred through the MTJ stack of layers. Methodologies have also been developed to control iso/dense line pattern collapse. However, the challenge is to apply existing photolithography techniques to MRAM MTJ fabrication. A process sequence is needed that enables two dimensional control of a MTJ post pattern having a CD of 100 nm or less while maintaining an adequate process latitude that does not suffer from pattern collapse.
In U.S. Pat. No. 6,984,529, a hard mask is patterned and then oxidized before the pattern is transferred through the MTJ stack of layers.
U.S. Pat. No. 7,067,866 describes a method of forming a MTJ element where the dimension of the MTJ element in the direction of a bit line is defined before a hard mask is deposited on the top surface. The hard mask is used to protect the MTJ element during a subsequent CMP process.